The prior art contains a number of switched-capacitor gain stage designs. Briefly, switched-capacitor gain stages provide precisely defined gains determined by a ratio in values between capacitors, and such gain stages are typically fabricated on a single integrated circuit.
In one type of switched-capacitor gain stage, a pair of capacitors is charged in parallel across an input voltage and a ground reference. The capacitor terminals that are coupled to the ground reference are then moved to the inverting input of an operational amplifier while one of the capacitor terminals previously coupled to the input voltage is switched to the output of the amplifier and the other capacitor terminal previously coupled to the input voltage is switched to a reference voltage. When the capacitors have the same value, the output of the amplifier will then be twice the input voltage, modified by the addition or subtraction of the reference voltage (depending upon the polarity of the reference voltage). In order to increase the throughput of the gain stage, two sets of capacitor pairs may be used with one charging from the input voltage while the other is connected to the operational amplifier to produce an output value.
A rapid and precise pipelined ADC can be created by connecting a number of these equal capacitor gain stages in series. The first gain stage receives the voltage to be converted and outputs a voltage to the next gain stage for its input, and so forth. Each gain stage doubles its respective input voltage, then adds a positive voltage reference, a negative voltage reference, or zero, as determined by a comparison of the input voltage with a high voltage reference or threshold (VH) and a low voltage reference or threshold (VL). Each gain stage also produces digital conversion output bits dependent on the threshold process and the output bits from the various gain stages are combined to produce the resultant digital conversion value. A gain stage suitable for use in such an ADC is described in U.S. Pat. No. 5,574,457.
Frequently there is a need to simultaneously convert two analog signals into their digital values, for example, in electronic systems having an “in-phase” signal component and a corresponding “quadrature” signal component. Such conversions may be accomplished through the use of two distinct ADCs, but at a considerable cost and power penalty. An alternative approach is to position two sample-and-hold circuits in front of a single ADC. The sample-and-hold circuits may simultaneously sample the two input values to be presented in an interleaved sequence to a single ADC for conversion. A drawback to this latter approach, however, is that it introduces additional circuitry between the signal inputs and the ADC, which can add noise or systematic errors to the resultant digital conversion value. Further, the buffer amplifiers, timing circuitry for the interleaving, and other circuitry required by the sample-and-hold circuits significantly increase the cost of the ADC.
Another approach for a pipelined ADC, which is disclosed in U.S. Pat. No. 6,362,770, employs an initial switched-capacitor gain stage that receives two analog input signals for simultaneous sampling. The initial gain stage performs both a sample-and-hold function and a most significant bit extraction. Although the ADC disclosed in U.S. Pat. No. 6,362,770 is capable of simultaneously converting two separate input voltage signals, the configuration of the initial stage may not be suitable for all ADC applications, particularly those that require high precision, high channel isolation, and precise input channel matching.
Accordingly, it is desirable to have an improved switched-capacitor gain stage that is capable of simultaneously sampling multiple analog input channels, precisely amplifying the input signals, and generating a single output of interleaved voltage samples corresponding to the multiple input channels. Such a switched-capacitor gain stage can be utilized in a pipelined ADC, thereby saving significant chip area and reducing power consumption relative to a conventional approach that employs a plurality of distinct ADC circuits. In addition, it is desirable to have a switched-capacitor gain stage that provides improved channel isolation, input channel load balancing, and increased accuracy relative to conventional multiple input gain stages. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.